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A new inter-core interconnect

Is a hierarchical state, the. Pu can also expand into multiple state transition combination. According to the rules of data scheduling Lee algorithm can be seen from Figure 2, data scheduling process. Hierarchical status of S122, that pass macroblock P (n, m) corresponding macroblock in the reference frame I (n, m): SIl1 corresponding to the upper left corner of the macro block I (n.1, m.1); SI33 Yong core question of a new interconnect Zhang Yu Dong March 2008 No. 1 39 (Total 130) l. . ·'-''·'''· A ... ... t '. __. _. ,[link widoczny dla zalogowanych], \~ propagate good .. scape. Man baskets Ji i. ... ... ~ ~. Fig. 2 lower right corner of the state of data input scheduling macro block I (n + l, m +1); inferior race analogy: SP said P macroblocks Biography (n, m). at all levels of the state should expand into a control sequence, to determine whether normal transmission, whether the region is just,[link widoczny dla zalogowanych], whether or not to suspend the transfer. For I frame, but also to judge, whether to the I-BUF had already passed the previous data, without having to repeat the transmission. Figure 2 describes the state of other simple shown in Table 1. Table l state of the state of the functional menu, so the initial state SD0NE1 a P block scheduling done to determine whether the subgraph of I-line leaf l complete. SLINE subgraph of I-line completion to determine whether the sub-graph complete scheduling decision under sub-graph to chart the direction of SBUPF a dispatch from the bottom up, ready to work under the sub-diagram from the parameters SBDoWN top-down scheduling, preparation of sub-transmission scheduling parameters S0VER1 5 Conclusion In this paper, calculation of the end of high-density type of image processing applications,[link widoczny dla zalogowanych], for example, discussed the \message queue based solutions,[link widoczny dla zalogowanych], including: shared data buffer,[link widoczny dla zalogowanych], a positive message queue and feedback channels. the core idea of this method is to ensure that multi-stage pipeline structure of \The design idea can be multiple-stage pipeline structure of the state in the kernel between the need for high throughput data transmission interconnection between the cores; also be applied to similar applications of chip-level interconnect, system board-level interconnect .
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